cy2907 single-pll general-purpose eprom programmable clock generator cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07137 rev. ** revised september 26, 2001 cyclocks is a trademark of cypress semiconductor corporation. features benefits single phase-locked loop architecture generates a custom frequency from an external source eprom programmability easy customization and fast turnaround factory-programmable (cy2907, cy2907i) or field-pro- grammable (cy2907f & cy2907fi) device options programming support available for all opportunities up to two configurable outputs provides clocking requirements from a single device low-skew, low-jitter, high-accuracy outputs meets critical industry standard timing requirements power management (power-down, oe) supports low-power applications frequency select option up to 16 user-selectable frequencies configurable 5v or 3.3v operation supports industry-standard design platforms 8-pin or 14-pin soic packages industry-standard packaging saves on board space selector guide part number outputs input frequency range output frequency range specifics cy2907 2 10 mhz ? 25 mhz (external crystal) 1 mhz ? 30 mhz (reference clock) 500 khz ? 130 mhz (5v) 500 khz ? 100 mhz (3.3v) factory programmable commercial temperature cy2907i 2 10 mhz ? 25 mhz (external crystal) 1 mhz ? 30 mhz (reference clock) 500 khz ? 100 mhz (5v) 500 khz ? 80 mhz (3.3v) factory programmable industrial temperature cy2907f8 cy2907f14 210 mhz ? 25 mhz (external crystal) 1 mhz ? 30 mhz (reference clock) 500 khz ? 100 mhz (5v) 500 khz ? 80 mhz (3.3v) field programmable commercial temperature cy2907f8i cy2907f14i 210 mhz ? 25 mhz (external crystal) 1 mhz ? 30 mhz (reference clock) 500 khz ? 90 mhz (5v) 500 khz ? 66.66 mhz (3.3v) field programmable industrial temperature xtalout xtalin refclk osc. 1 2 3 4 5 6 7 10 9 8 11 14 13 12 top view s1 s2 s3 v ss v ss pd xtalin s0 refclk v dd clka oea oer xtalout clka pll eprom table s0 s1 14-pin soic s2 s3 oer output multiplexer and dividers pd 1 2 3 4 5 8 7 6 s0 v ss xtalin xtalout refclk v dd clka s1 8-pin soic configuration eprom and test logic oea logic block diagram pin configurations [+] feedback
cy2907 document #: 38-07137 rev. ** page 2 of 10 functional description the cy2907 is a general-purpose clock generator designed for use in a wide variety of applications ? from graphics to pc peripherals to disk drives. it generates selectable system clock frequencies from a single reference input (crystal or reference clock). the cy2907 is configured with an eprom array, much like the other devices in the cypress eprom programmable clock family, making it easily customizable for any applica- tion. furthermore, the cy2907 is compatible with all indus- try-standard 9107 and 9108 clock synthesizers. cyclocks? software cyclocks is an easy-to-use software application that allows you to configure any one of the eprom programmable clocks offered by cypress. you may specify the input frequency, pll and output frequencies, and different functional options. please note the output frequency ranges in this data sheet when specifying them in cyclocks to ensure that you stay within the limits. you can download a copy of cyclocks free on the cypress semiconductor website at www.cypress.com. consider using the cy2081, cy2291, or cy2292 for applica- tions that require unrelated and multiple output frequencies. consider using the cy2071a for applications that require more than one output clock. cypress ftg programmer the cypress frequency timing generator (ftg) program- mers are portable programmers designed to custom program our family of eprom field programmable clock devices. the ftg programmers connect to a pc serial port and allow users of cyclocks software to quickly and easily program any of the cy2291f, cy2292f, cy2071af, and cy2907f devices. the ordering code for the cypress ftg programmer is cy3670. maximum ratings (beyond which the useful life may be impaired. for user guide- lines, not tested.) supply voltage ................................................. ? 0.5 to +7.0v input voltage ........................................... ? 0.5v to v dd +0.5v storage temperature (non-condensing) ... ? 65 c to +150 c max. soldering temperature (10 sec) ...................... +260 c junction temperature............................................... +150 c static discharge voltage ........................................... >2000v (per mil-std-883, method 3015) pin summary name pin number description 14-pin soic 8-pin soic s1 1 5 frequency select (clka) (internal pull-up resistor to v dd ) s2 2 na frequency select (clka) (internal pull-up resistor to v dd ) s3 3 na frequency select (clka) (internal pull-up resistor to v dd ) v ss 4 2 ground v ss 5 na ground pd 6 na power-down (active low) (internal pull-up resistor to v dd ) xtalin [1] 7 3 reference crystal input xtalout [1, 2] 8 4 reference crystal feedback oer 9 na refclk output enable (active high) (internal pull-up resistor to v dd ) oea 10 na clka output enable (active high) (internal pull-up resistor to v dd ) clka 11 6 clock output v dd 12 7 voltage supply refclk 13 8 reference clock output (default, can be driven by pll if desired) s0 14 1 frequency select (clka) (internal pull-up resistor to v dd ) notes: 1. for best accuracy, use a parallel-resonant crystal, c load 17 pf. 2. float xtalout pin if xtalin is driven by reference clock (as opposed to crystal). [+] feedback
cy2907 document #: 38-07137 rev. ** page 3 of 10 operating conditions [3] parameter description min. max. unit v dd supply voltage, 5v operation 4.5 5.5 v supply voltage, 3.3v operation 3.0 3.6 v t a commercial operating temperature, ambient 0 70 c industrial operating temperature, ambient ? 40 85 c c l max. capacitive load 15 pf f ref external reference crystal 10.0 25.0 mhz external reference clock [4, 5] 1.0 30.0 mhz electrical characteristics at 5.0v commercial v dd = 4.5v to 5.5v, t a = 0 c to +70 c parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs 2.0 v v il low-level input voltage except crystal inputs 0.8 v v oh [4] high-level output voltage v dd = v dd min. i oh = ? 30 ma clka 2.4 v v ol [4] low-level output voltage v dd = v dd min. i ol = 10 ma clka 0.4 v i oh [4] output high current v oh = 2.0v ? 35 ma i ol [4] output low current v ol = 0.8v 22 ma i ih input high current v ih = v dd ? 2 2 a i il input low current v il = 0v 20 a i dd [5] power supply current pd high, clka = 50 mhz 42 ma i dd power supply current pd low, logic inputs low 100 a i dd power supply current pd low, logic inputs high 40 a r pu [4] pull-up resistor v in = v dd ? 1.0 v 700 k ? electrical characteristics at 3.3v commercial v dd = 3.0v to 3.6v, t a = 0 c to +70 c parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs 0.7*v dd v v il low-level input voltage except crystal inputs 0.2*v dd v v oh [4] high-level output voltage clka, i oh = ? 5 ma 0.85*v dd v v ol [4] low-level output voltage clka, i ol = 6 ma 0.1*v dd v i oh [4] output high current v oh = 0.7*v dd ? 10 ma i ol [4] output low current v ol = 0.2*v dd 15 ma i ih input high current v ih = v dd ? 2 2 a i il input low current v il = 0v 10 a i dd [5] power supply current pd high, clka = 50 mhz 40 ma i dd power supply current pd low, logic inputs low 40 a i dd power supply current pd low, logic inputs high 12 a r pu [4] pull-up resistor v in = v dd ? 0.5v 900 k ? notes: 3. electrical parameters are guaranteed with these operating conditions. 4. guaranteed by design, not 100% tested in production. 5. load = max. typical configuration, f ref = 14.318 mhz. specific configurations may vary. a close approximation of i dd can be derived by the following formula: i dd (ma) = v dd * (6.25 + (0.055*f ref ) + (0.0017*c load *(f clka + refclk))). c load is specified in pf and f is specified in mhz. [+] feedback
cy2907 document #: 38-07137 rev. ** page 4 of 10 electrical characteristics at 5.0v industrial v dd = 4.5v to 5.5v, t a = ? 40 c to +85 c parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs 2.0 v v il low-level input voltage except crystal inputs 0.8 v v oh [4] high-level output voltage v dd = v dd min. i oh = ? 30 ma clka 2.4 v v ol [4] low-level output voltage v dd = v dd min. i ol = 10 ma clka 0.4 v i oh [4] output high current v oh = 2.0v ? 45 ma i ol [4] output low current v ol = 0.8v 20 ma i ih input high current v ih = v dd ? 2 2 a i il input low current v il = 0v 20 a i dd [5] power supply current pd high, clka = 50 mhz 54 ma i dd power supply current pd low, logic inputs low 110 a i dd power supply current pd low, logic inputs high 45 a r pu [4] pull-up resistor v in = v dd ? 1.0 v 700 k ? electrical characteristics at 3.3v industrial v dd = 3.0v to 3.6v, t a = ? 40 c to +85 c parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs 0.7*v dd v v il low-level input voltage except crystal inputs 0.2*v dd v v oh [4] high-level output voltage clka, i oh = ? 5 ma 0.85*v dd v v ol [4] low-level output voltage clka, i ol = 6 ma 0.1*v dd v i oh [4] output high current v oh = 0.7*v dd ? 12 ma i ol [4] output low current v ol = 0.2*v dd 14 ma i ih input high current v ih = v dd ? 22 a i il input low current v il = 0v 10 a i dd [5] power supply current pd high, clka = 50 mhz 50 ma i dd power supply current pd low, logic inputs low 50 a i dd power supply current pd low, logic inputs high 15 a r pu [4] pull-up resistor v in = v dd ? 0.5v 900 k ? [+] feedback
cy2907 document #: 38-07137 rev. ** page 5 of 10 switching characteristics at 5.0v commercial [4] parameter output [6] description test conditions min. max. unit t r clka output rise time 0.8v to 2.0v 15-pf load 1.40 ns t f clka output fall time 2.0v to 0.8v 15-pf load 1.00 ns t r clka output rise time 20% to 80% 15-pf load 3.5 ns t f clka output fall time 80% to 20% 15-pf load 2.5 ns t d clka duty cycle 15-pf load at 1.4v 45.0 55.0 % f i xtalin input frequency crystal oscillator 10 25 mhz f i xtalin input frequency external input clock [7] 1 30 mhz f o clka output frequency cy2907, 15-pf load 0.5 130.0 mhz cy2907f, 15-pf load 0.5 100.0 mhz t jis clka jitter (one sigma) 20 mhz to 130 mhz 150 ps t jis clka jitter (one sigma) 14 mhz to 20 mhz 200 ps t jis clka jitter (one sigma) less than 14 mhz 1 % t jab clka jitter (absolute) 20 mhz to 130 mhz ? 250 + 250 ps t jab clka jitter (absolute) 14 mhz to 20 mhz ? 500 + 500 ps t jab clka jitter (absolute) less than 14 mhz 3 % t pu power-up time 18 ms t ft clka transition time 8 mhz to 66.6 mhz 13 ms switching characteristics at 3.3v commercial [4] parameter output [6] description test conditions min. max. unit t r clka output rise time 20% to 80% 15-pf load 3.5 ns t f clka output fall time 80% to 20% 15-pf load 2.5 ns t d clka duty cycle 15-pf load at 1.4v 40.0 53.0 % f i xtalin input frequency crystal oscillator 10 25 mhz f i xtalin input frequency external input clock [7] 130mhz f o clka output frequency cy2907, 15-pf load 0.5 100.0 mhz cy2907f, 15-pf load 0.5 80.0 mhz t jis clka jitter (one sigma) 25 mhz to 100 mhz 150 ps t jis clka jitter (one sigma) 14 mhz to 25 mhz 200 ps t jis clka jitter (one sigma) less than 14 mhz 1 % t jab clka jitter (absolute) 25 mhz to 120 mhz ? 250 +250 ps t jab clka jitter (absolute) 14 mhz to 25 mhz ? 500 +500 ps t jab clka jitter (absolute) less than 14 mhz 3 % t pu power-up time 18 ms t ft clka transition time 8 mhz to 66.6 mhz 13 ms notes: 6. refclk output can also be configured to be driven by the pll, in which case the above characteristics are valid. 7. please refer to the application note ? crystal oscillator topics ? when using an external reference clock as an input frequency source. : [+] feedback
cy2907 document #: 38-07137 rev. ** page 6 of 10 switching characteristics at 5.0v industrial parameter output [6] description test conditions min. max. unit t r clka output rise time 0.8v to 2.0v 15-pf load 1.40 ns t f clka output fall time 2.0v to 0.8v 15-pf load 1.00 ns t r clka output rise time 20% to 80% 15-pf load 3.5 ns t f clka output fall time 80% to 20% 15-pf load 2.5 ns t d clka duty cycle 15-pf load at 1.4v 45.0 55.0 % f i xtalin input frequency crystal oscillator 10 25 mhz f i xtalin input frequency external input clock [7] 1 30 mhz f o clka output frequency cy2907, 15-pf load 0.5 100.0 mhz cy2907f, 15-pf load 0.5 90 mhz t jis clka jitter (one sigma) 20 mhz to 130 mhz 150 ps t jis clka jitter (one sigma) 14 mhz to 20 mhz 200 ps t jis clka jitter (one sigma) less than 14 mhz 1 % t jab clka jitter (absolute) 20 mhz to 130 mhz ? 250 + 250 ps t jab clka jitter (absolute) 14 mhz to 20 mhz ? 500 + 500 ps t jab clka jitter (absolute) less than 14 mhz 3 % t pu power-up time 18 ms t ft clka transition time 8 mhz to 66.6 mhz 13 ms switching characteristics at 3.3v industrial parameter output [6] description test conditions min. max. unit t r clka output rise time 20% to 80% 15-pf load 3.5 ns t f clka output fall time 80% to 20% 15-pf load 2.5 ns t d clka duty cycle 15-pf load at 1.4v 40.0 53.0 % f i xtalin input frequency crystal oscillator 10 25 mhz f i xtalin input frequency external input clock [7] 1 30 mhz f o clka output frequency cy2907i, 15-pf load 0.5 80.0 mhz cy2907fi, 15-pf load 0.5 66.6 mhz t jis clka jitter (one sigma) 25 mhz to 100 mhz 150 ps t jis clka jitter (one sigma) 14 mhz to 25 mhz 200 ps t jis clka jitter (one sigma) less than 14 mhz 1 % t jab clka jitter (absolute) 25 mhz to 120 mhz ? 250 +250 ps t jab clka jitter (absolute) 14 mhz to 25 mhz ? 500 +500 ps t jab clka jitter (absolute) less than 14 mhz 3 % t pu power-up time 18 ms t ft clka transition time 8 mhz to 66.6 mhz 13 ms [+] feedback
cy2907 document #: 38-07137 rev. ** page 7 of 10 switching waveforms 2907 ? 3 frequency select change (transition time) f old select clka t ft old select new select stable f new 2907 ? 4 duty cycle timing 2907 ? 5 1.4v t 2 clka t 1 t d =t 2 t 1 all outputs rise/fall time 2907 ? 6 clka t r 20% 80% t f test circuit clka v dd c load outputs note: all capacitors should be placed as close to each pin as possible. 0.1 f v dd refclk c load [+] feedback
cy2907 document #: 38-07137 rev. ** page 8 of 10 ordering information ordering code package name package type operating range cy2907sc-xxx s8, s14 8-pin or 14-pin soic 5.0v, commercial, factory programmable cy2907sl-xxx s8, s14 8-pin or 14-pin soic 3.3v, commercial, factory programmable cy2907si-xxx s8, s14 8-pin or 14-pin soic 5.0v/3.3v, industrial, factory programmable cy2907f8 s8 8-pin soic 5.0v/3.3v, commercial, field programmable cy2907f8i s8 8-pin soic 5.0v/3.3v, industrial, field programmable cy2907f14 s14 14-pin soic 5.0v/3.3v, commercial, field programmable cy2907f14i s14 14-pin soic 5.0v/3.3v, industrial, field programmable cy3670 cypress ftg programmer custom programming for field programmable clocks package characteristics package ja (c/w) jc (c/w) transistor count 8-pin soic 170 35 5436 14-pin soic 140 31 5436 package diagrams 8-lead (150-mil) soic s8 51-85066-a [+] feedback
cy2907 document #: 38-07137 rev. ** page 9 of 10 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 14-lead (150-mil) soic s14 51-85067-a [+] feedback
cy2907 document #: 38-07137 rev. ** page 10 of 10 document title: cy2907 single-pll general-purpose eprom programmable clock generator document number: 38-07137 rev. ecn no. issue date orig. of change description of change ** 110246 12/18/01 szv change from spec number: 38-00505 to 38-07137 [+] feedback
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